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.ltr "Dr. J. C. R. Licklider, Director";
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%3Subject:∂9%1Proposal for Supplementary Capital Equipment Funding (Contract
DAHC15-73-C-0435)

Dear Lick:

This is a proposal to supplement the subject contract by $130,000 to
permit the purchase of add-on memory for our computer system.

.cb PROBLEM
The PDP-10 timesharing system at the Stanford Artificial Intelligence
Laboratory uses a single KA-10 processor
with 256k of core memory made up of three different types.  Some
of this memory is rather old (1966 vintage) and three-fourths of it
is slow by modern standards (2 microsecond cycle time).

The processing demands of several of our research projects are not
being met by the existing system, even though it makes very
efficient use of the available resources.  Some of the computer vision
and robotics programs have been partitioned into two or more segments
to get around memory size limitations, but this creates communication
difficulties between the segments, which in turn has the effect of substantially
increasing
both human and computer time needed to accomplish a given task.

Memory shortage problems are even more acute in our Mathematical Theory
of Computation work.  Research with LCF (Logic of Computable Functions)
is severely hampered by the necessity of breaking Lisp programs into
multiple parts, for lack of sufficient main memory.  Because of the
nature of the Lisp system, these parts cannot be made to communicate
effectively.

Typical core images of FOL (First Order Logic)
programs exceed 80,000 words and we frequently have as many as five
people running such programs at once.  With the existing memory
size, each of these large jobs must be swapped out before the next
can be brought it.  The effect is to severely degrade response
times, which in turn  frustrates or
effectively halts progress in some areas.

.CB PROPOSED SOLUTION
We propose to purchase a 256k x 37 bit memory with 1 microsecond cycle
time.  This will have at least three beneficial effects:
.bs
1) The larger memory will permit research to proceed in certain areas
that are out of reach in the current system do to limitations on user core,

2)  the increased capacity will reduce the amount
of swapping needed under heavy load conditions (particularly when
several large jobs are running), and

3)  the faster memories will more fully exploit the performance of
the KA-10 processor.
.end

Looking further ahead, we will likely have to increase processor
performance also, most likely by the acquisition of a KL-10 or equivalent processor.
Consequently, any memory that is purchased now should be compatible
with such a step.

In consideration of these objectives, we require memories with the
following characteristics:
.bs; crbreak;
1) 1 microsecond cycle time or less;
2) 256k * 37 bits divided into at least four units that can be cycled independently;
3) 8 or more memory ports compatible with KL-10 memory busses.
.end

We have surveyed the market and find that the least expensive
memories meeting these requirements cost
$130,000.  The University is unable to provide funds
from its own resources to make this purchase, so we request additional
funding from ARPA to make this purchase possible.

.skip;GROUP;
Sincerely,
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John McCarthy
Principal Investigator
.APART

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